How to reduce interrupt latency when using uCOS-II?

This forum is for users of Atmel's SAM Series and who are interested in using µC/OS-II, The Real-Time Kernel.

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How to reduce interrupt latency when using uCOS-II?

Tue Dec 16, 2008 11:41 am


I am looking for ways to reduce interrupt latency when using uCOS-II. I am working with an AT91SAM7S running at 24 MHz.

The background: My application needs to respond to a received UART byte within 12.5 us, which includes some (minor) processing of the received byte and sending out an answer.

Right now, I am using the SAM7S port v. 1.84. and enable interrupt nesting by using the sequence

Code: Select all

(*pfnct)(); /* Execute the ISR for the interrupting device              */
in OS_CPU_ExceptHndlr. The UART interrupt has the priority AT91C_AIC_PRIOR_HIGHEST, the other active interrupts (PIT and SPI) use lower priorities. The firmware uses three tasks, two mailboxes to communicty between ISRs and tasks, and one mutex for communication between two tasks.

On average, the latency (end of parity bit of received byte to start bit of transmitted byte) is about 12.3 us, however, the latency varies between 6.4 us and 20.4 us.

Any advice on how to reduce the maximum latency?

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