Parallel Capture Mode with PDC

Discussion around product based on ARM Cortex M3 core.

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chriswedge
Posts: 6
Joined: Thu Oct 07, 2010 3:45 pm

Parallel Capture Mode with PDC

Tue Oct 26, 2010 3:55 pm

I'm using a SAM3S, still using the EK. The processor crystal is 12MHz, and this is generating a Master Clock of 64MHz. The requirement is to clock data from an 8-bit A2D at 16.666MHz, so I've set up the Parallel Capture Mode with the PDC, as described on page 492 (section 27.5.13.4).

However, I can't get the system to run above 8.5MHz. To test my capture driver I've wired up a 74HC4040 counter and programmed PCK0 to be a division of PLLB. This clocks the counter. At 8.5MHz (MUL = 17, DIV = 3, PrgCLK_DivideBy8) I get all the counters. At 9 MHz, I'm missing some.

27.5.13.3 says "Frequency of PIO controller clock must be strictly superior to 2 times the frequency of the clock of the device which generates the parallel data." so with the master clock running at 64MHz I should be able to clock data in and anything less than 32MHz.

Help!

Chris Wedge
bdenis
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Posts: 48
Joined: Tue Feb 08, 2005 1:56 pm

Re: Parallel Capture Mode with PDC

Tue Oct 26, 2010 11:43 pm

chriswedge wrote:I'm using a SAM3S, still using the EK. The processor crystal is 12MHz, and this is generating a Master Clock of 64MHz. The requirement is to clock data from an 8-bit A2D at 16.666MHz, so I've set up the Parallel Capture Mode with the PDC, as described on page 492 (section 27.5.13.4).

However, I can't get the system to run above 8.5MHz. To test my capture driver I've wired up a 74HC4040 counter and programmed PCK0 to be a division of PLLB. This clocks the counter. At 8.5MHz (MUL = 17, DIV = 3, PrgCLK_DivideBy8) I get all the counters. At 9 MHz, I'm missing some.

27.5.13.3 says "Frequency of PIO controller clock must be strictly superior to 2 times the frequency of the clock of the device which generates the parallel data." so with the master clock running at 64MHz I should be able to clock data in and anything less than 32MHz.

Help!

Chris Wedge

Hi Chris,

Have you set DSIZE to 2 ? It shall increase the bandwith. I suppose you use the internal SRAM for the datas?

Regards,

bdenis
chriswedge
Posts: 6
Joined: Thu Oct 07, 2010 3:45 pm

Re: Parallel Capture Mode with PDC

Wed Oct 27, 2010 1:14 pm

Thanks, that's nearly there now! Remember to align RPR on a word boundary and RCR is the number of words, not bytes. Also don't set DSIZE to 3! (Yes I am using internal SRAM)

However, I'm getting data in a strange order. Assuming counts a b c d I'm seeing b a d c or x b a d. All the counts are there, it's just the order.
Chris

PS This is a clock speed issue. Halve the clock speed (back at 8.5MHz) and it's all OK.

**Suspecting it's the counter as it's value dependent. Will try a different counter and come back tomorrow**

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