SPI's NPCSx Selection

Discussion around product based on ARM Cortex M3 core.

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Workalot
Posts: 12
Joined: Sun Nov 14, 2010 2:39 am

SPI's NPCSx Selection

Thu Sep 22, 2011 12:08 pm

Section 30.6.1, page 581 of the SAM3S Preliminary datasheet nominates the PIO lines used for NPCSx use. How does one discern the choice of NPCS3 amongst PA3, PA5, PA22 when all exist as peripheral B on PIOA?
incognito
Posts: 32
Joined: Tue Jul 13, 2010 12:54 pm

Re: SPI's NPCSx Selection

Thu Sep 22, 2011 4:21 pm

Normally the NPCS and other lines are multiplexed wit a range of other pins to allow you to connect a custom set of devices to the processor without losing functionality. The three available pins for NPCS3 gives you a choice. Either 2 USARTS and the NPCS3 line or a USART, TWI and NPCS3 pin

Choose a pin that supports the NPCS3 as peripheral B (Note any errata) and the set of devices you want to use, connect your peripheral to the pin. Configure that specific pin, and only that one to be NPCS3 in your code.
Workalot
Posts: 12
Joined: Sun Nov 14, 2010 2:39 am

Re: SPI's NPCSx Selection

Fri Sep 23, 2011 12:42 am

Thank you incognito.

Yes I do understand pin multiplexing. I am wondering if in fact, in the case of NPCS3, there are three lines internally connected to the SPI engine which will all assert simultaneously. Which line is connected to a pin is done according to taste. And does this lead to the possibility of having two (or all three) lines connected to pins? A scenario which is not useful of course.

My purpose of this thread is to get me some clarity in understanding.

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