I am trying to achieve maximum performace in transfering data from internal SRAM to an external Memory (FPGA device).
At the moment i get with DMAC and SMC around 100 Mbps with following configuration:
- memory2memory transfer
- mcu at 96 MHz
- 16 bit smc transfer width
- bus lock, interface lock
- dma channel 4
There is still the possibility to shrink the smc cycles but i think the dma-c is already the bottle neck.
Between every transfer cycle (chip select low) there is a small pause and after 4 pulses there is a longer pause. Hence the pauses mainly determine the datarate.
Anyone has some expierence how to tune the transfer?