No CLK signal on SPI0

Discussion around product based on ARM Cortex M3 core.

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cmcraeslo
Posts: 9
Joined: Wed Mar 19, 2014 11:16 pm

No CLK signal on SPI0

Thu Oct 23, 2014 9:44 pm

Hello all,

I've been struggling with SAM3x8C and SPI for a couple of days now and can't seem to get it to work. Whatever I do with the software, I get no CLK signal on the SPI line. I worked with 8 bit microcontrollers for more than 10 year and things like SPI were really trivial.. but here, it's mad :)

I'm checking the CLK line with scope and see no activity. Not even on the CS line.

This is my code:

Code: Select all


sysclk_init();

ioport_set_pin_dir(PIO_PA27_IDX, IOPORT_DIR_OUTPUT); // SCK
ioport_set_pin_dir(PIO_PA25_IDX, IOPORT_DIR_INPUT); // MISO
ioport_set_pin_dir(PIO_PA26_IDX, IOPORT_DIR_OUTPUT); // MOSI
ioport_set_pin_dir(PIO_PA28_IDX, IOPORT_DIR_INPUT); // CS

#define SPI_CHIP_SEL 0
#define SPI_CHIP_PCS spi_get_pcs(SPI_CHIP_SEL)

pmc_enable_periph_clk(ID_SPI0);

spi_disable(SPI0);
spi_reset(SPI0);
spi_set_lastxfer(SPI0);
spi_set_master_mode(SPI0);
spi_disable_mode_fault_detect(SPI0);
spi_set_fixed_peripheral_select(SPI0);
spi_disable_peripheral_select_decode(SPI0);		
spi_set_peripheral_chip_select_value(SPI0, SPI_CHIP_PCS);	
spi_set_clock_polarity(SPI0, SPI_CHIP_SEL, SPI_CLK_POLARITY);
spi_set_clock_phase(SPI0, SPI_CHIP_SEL, SPI_CLK_PHASE);
spi_set_bits_per_transfer(SPI0, SPI_CHIP_SEL, SPI_CSR_BITS_8_BIT);
spi_set_baudrate_div(SPI0, SPI_CHIP_SEL, spi_calc_baudrate_div(10000, sysclk_get_cpu_hz()));
spi_set_transfer_delay(SPI0, SPI_CHIP_SEL, 0, 0);	
spi_configure_cs_behavior(SPI0, SPI_CHIP_SEL, SPI_CS_KEEP_LOW);
spi_enable(SPI0);

while(1)
{
  x++;
  spi_write_single(SPI0, x);
  delay_ms(100);
}
Any help would be appreciated. Thanks!
jharley
Posts: 238
Joined: Thu Dec 06, 2012 6:40 am

Re: No CLK signal on SPI0

Fri Oct 24, 2014 6:25 am

Code: Select all

ioport_set_pin_dir(PIO_PA27_IDX, IOPORT_DIR_OUTPUT); // SCKA
ioport_set_pin_dir(PIO_PA25_IDX, IOPORT_DIR_INPUT); // MISOA
ioport_set_pin_dir(PIO_PA26_IDX, IOPORT_DIR_OUTPUT); // MOSIA
ioport_set_pin_dir(PIO_PA28_IDX, IOPORT_DIR_INPUT); // CSA
Most IO ports a mux'd, to enable the pins for a function use the gpio_configure_pin() function *not* ioport_set_pin_dir() function... e.g.

Code: Select all

gpio_configure_pin(PIO_PA27_IDX, PIO_PERIPH_A | PIO_DEFAULT); // SCKA
gpio_configure_pin(PIO_PA25_IDX, PIO_PERIPH_A | PIO_DEFAULT); // MISOA
gpio_configure_pin(PIO_PA26_IDX, PIO_PERIPH_A | PIO_DEFAULT); // MOSIA
gpio_configure_pin(PIO_PA28_IDX, PIO_PERIPH_A | PIO_DEFAULT); // CSA
cmcraeslo
Posts: 9
Joined: Wed Mar 19, 2014 11:16 pm

Re: No CLK signal on SPI0

Fri Oct 24, 2014 10:23 am

Hi. Thanks for replying. I tried that, but it still doesn't work. Do you maybe have a working example of the SAM3x SPI code that works 100% ? Maybe it could be a hardware problem? Thanks!
jharley
Posts: 238
Joined: Thu Dec 06, 2012 6:40 am

Re: No CLK signal on SPI0

Fri Oct 24, 2014 3:02 pm

If you are using AS and the ASF i would recommend trying one of the example solutions. ;)
cmcraeslo
Posts: 9
Joined: Wed Mar 19, 2014 11:16 pm

Re: No CLK signal on SPI0

Fri Oct 24, 2014 3:03 pm

I did. All of them. None of them worked :(

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