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AT070TN92 & SAM3S || 24bit parallel RGB interface

Posted: Tue Nov 04, 2014 2:13 am
by lonka
Hey Guys,

I am interested in writing a driver for a 24bit parallel RGB interface. 
Probably the SAM3(running at 64Mhz) is to slow for the AT070TN92(normaly running at 32Mhz - 60 frames/sec) but I think the Display will also run with 16Mhz and 30 frames/sec. 

My idea is to generate the HSYNC and VSYNC signals by counters triggering an interrupt.

Is there someone with experience in writing such drivers? :roll:

AT070TN92 Datasheet:
https://docs.google.com/file/d/0B9cAzTd ... NGbHc/edit

Re: AT070TN92 & SAM3S || 24bit parallel RGB interface

Posted: Tue Nov 04, 2014 5:49 pm
by jharley
lonka wrote:Is there someone with experience in writing such drivers? :roll:
Most certainly there is!

Typically you will want to use a LCD Controller chip that the SAM can talk to. If your goal is to roll your own controller for this LCD panel... then an FPGA is better suited for this function.

Re: AT070TN92 & SAM3S || 24bit parallel RGB interface

Posted: Wed Nov 05, 2014 1:47 am
by lonka
The master plan to reach my firs main goal step by step:

Step 1: (DCLK) Generate a clock for the dispaly (32MHz)

According to the datasheet of the dispaly...
This display has a resolution of 800x480.

Let's take a look at the horizontal display area:

My total clocks per line (th) = H Blanking (thb) + Active Area (thd) + H Front Porch (thfp)
     th = thb + thd + thfp
     th = 46 + 800 + 16...354 (let's take for thfp the typical value from the datasheet... 210)
     th = 46 + 800 + 210 = 1056 [clocks/line]


Step 2: (HSYNC) generate a pulse (pulse width max. 40 clocks) every 1056 clocks

Now the vertical display area:
     Total lines (tv) = VS Blanking (tvb) + Vertical Display Area (tvd) + VS Front Porch (tvfp)
     tv = 23 + 480 + 7...147 (let's take for thfp the typical value from the datasheet... 22)
     tv = 23 + 480 + 22 = 525 [lines]


Step 3: (VSYNC) generate a pulse (pulse width max. 20 lines) every 525 lines


Step 4: (DE) Enable Data only in active area.

     The cursor is in the
          Horizontal active area:
          46 clocks afer the falling edge of HSYNC for 800 clocks 

          Vertical active area:
          23 lines afer the falling edge of VSYNC for 480 lines


The first main goal is to set all pixel in to a red color!
I am going to post my code step by step. So you can see my progress and maybe give me a hand.

Re: AT070TN92 & SAM3S || 24bit parallel RGB interface

Posted: Wed Nov 05, 2014 2:17 am
by lonka
Step 1: (DCLK) Generate a clock for the dispaly (32MHz)

Code: Select all


int main (void)
{
	/*system clock is set to 64MHz*/
	sysclk_init();
	lcd_clk_init();
	pio_init();
	
	while (1)
	{
	}
}

void lcd_clk_init(void)
	{
		pio_set_peripheral(PIOA, PIO_PERIPH_B, PIO_PA17);
		
		/*Switch the Programmable Clock module PCK1 source clock to the MAIN Clock, with a prescaler of 2:*/
		pmc_switch_pck_to_pllack(PMC_PCK_1, PMC_PCK_PRES_CLK_4);
			
		/*Enable Programmable Clock module PCK1:*/
		pmc_enable_pck(PMC_PCK_1);								
	}

void pio_init(void)
{
	/*Enable the module clock to the PIOA peripheral*/
	pmc_enable_periph_clk(ID_PIOA);	
}
Now I have my DCLK signal on PA17.

Step 2: (HSYNC) generate a pulse (pulse width max. 40 clocks) every 1056 clocks

Here starts the first problem: 
 I have to count to 1056 and trigger an interrupt. 
 So I would take a counter and trigger an interrupt on a Register Compare Match  like I did it before on AVRs. But that's so confusing on SAM3 :oops:  
 

Re: AT070TN92 & SAM3S || 24bit parallel RGB interface

Posted: Thu Nov 06, 2014 9:17 pm
by lonka
I created a repository on GitHub for this project
https://github.com/lonka1990/LBdev.git

Here is some timing information in addition to my last post.

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