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SAM3A4C DMA issue, BTSIZE max is 4095??

Posted: Sat Jan 24, 2015 5:16 am
by ahgu
I am doing DMA from SPI to SRAM, 
works great when BTSIZE is less than 4096,
stops working when BTSIZE is 4096, and incomplete data when BTSIZE is larger than 4096, I need about 7638 in this case. 

    status=AT91C_BASE_HDMA->DMAC_EBCISR; //clear
    status=status;
    AT91C_BASE_HDMA->DMAC_CH_NUM[HDMA_CHANNEL].DMAC_SADDR = (unsigned int) & (pSpi->SPI_RDR);




    AT91C_BASE_HDMA->DMAC_CH_NUM[HDMA_CHANNEL].DMAC_CFG = AT91C_HDMA_SRC_PER_2 |
              DMAC_CFG_SRC_H2SEL_HW |
              DMAC_CFG_SOD_ENABLE | DMAC_CFG_FIFOCFG_ALAP_CFG;




    AT91C_BASE_HDMA->DMAC_CH_NUM[HDMA_CHANNEL].DMAC_DSCR = 0;
    //AT91C_BASE_HDMA->HDMA_CH[0].HDMA_CTRLA |= 0xFF; //PIXELS ;
    AT91C_BASE_HDMA->DMAC_CH_NUM[HDMA_CHANNEL].DMAC_CTRLA = 7638  |DMAC_CTRLA_SCSIZE_CHK_1| DMAC_CTRLA_DCSIZE_CHK_1|DMAC_CTRLA_SRC_WIDTH_HALF_WORD | DMAC_CTRLA_DST_WIDTH_WORD;
    AT91C_BASE_HDMA->DMAC_CH_NUM[HDMA_CHANNEL].DMAC_CTRLB = DMAC_CTRLB_SRC_DSCR_FETCH_DISABLE | DMAC_CTRLB_DST_DSCR_FETCH_DISABLE |
            DMAC_CTRLB_FC_PER2MEM_DMA_FC |
            DMAC_CTRLB_SRC_INCR_FIXED |
            DMAC_CTRLB_DST_INCR_INCREMENTING;




    AT91C_BASE_HDMA->DMAC_CH_NUM[HDMA_CHANNEL].DMAC_DADDR = (unsigned int) ptr_dma[data_head];
    AT91C_BASE_HDMA->DMAC_EN = DMAC_EN_ENABLE;
    AT91C_BASE_HDMA->DMAC_CHER = DMAC_CHER_ENA3 ;
    IRQ_EnableIT(ID_DMAC);

Re: SAM3A4C DMA issue, BTSIZE max is 4095??

Posted: Sat Jan 24, 2015 6:12 pm
by ahgu
seems the limit is 4095, if you set btsize to (4096+X), it only DMA X numbers. 
how to get around? I need to get 7368 numbers.