UART and PDC issue with ENDTX interrupt

Discussion around product based on ARM Cortex M3 core.

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mach
Posts: 4
Joined: Fri Jul 31, 2015 2:15 pm

UART and PDC issue with ENDTX interrupt

Sat Aug 01, 2015 9:59 pm

I'd like to send debug messages via UART with DMA transfer using the ASF. I used AT08642 Application Note as reference. However, the ENDTX interrupt does not stop to fire. I'm using a SAM3S MCU with ASF 3.19. The code looks roughly like this:

Code: Select all

Pdc *uart_pdc = NULL;

void UART1_Handler(void)
{
	uint32_t status = uart_get_status(UART1);

	if ( status & UART_SR_ENDTX ) {
		pdc_disable_transfer( uart_pdc, PERIPH_PTCR_TXTDIS );
	}
}

void init() {
	uart_pdc = uart_get_pdc_base(UART1);
	uart_enable_interrupt(UART1, UART_IER_ENDTX);
	NVIC_EnableIRQ(UART1_IRQn);
}

void send_msg( uint8_t *buf, size_t size ) {
	uart_tx_packet.ul_addr = buf;
	uart_tx_packet.ul_size = size;

	pdc_tx_init(uart_pdc, &uart_tx_packet, NULL);
	pdc_enable_transfer( uart_pdc, PERIPH_PTCR_TXTEN );
}
I've seen examples in the internet, where they clear pending interrupts in the NVIC. Is that necessary? I would expect that it's enough to disable to TX transfer in order to stop ENDTX from fireing again?!
blue_z
Location: USA
Posts: 2035
Joined: Thu Apr 19, 2007 10:15 pm

Re: UART and PDC issue with ENDTX interrupt

Tue Aug 04, 2015 7:31 pm

mach wrote:I would expect that it's enough to disable to TX transfer in order to stop ENDTX from fireing again?!
You have evidence that your expectation is incorrect.
FWIW atmel_serial.c for Linux disables both the PDC transfer and the interrupts.
Or study section 24.4.5.2 Transmit Transfer End of the SAM3S datasheet to properly reset the source of this interrupt.

mach wrote:However, the ENDTX interrupt does not stop to fire.
Your phrasing barely makes sense.
You should be reporting what you actually observe rather than tell us what you think is not occurring.

Regards
mach
Posts: 4
Joined: Fri Jul 31, 2015 2:15 pm

Re: UART and PDC issue with ENDTX interrupt

Wed Aug 05, 2015 1:27 pm

Thanks for the reply blue_z. It turned out that a major problem were wrong interrupt priorities in NVIC. But I changed my code now to enable interrupts and transfer in my write() function and disable interrupts in the interrupt handler - as you mentioned. And now it works fine.

I also discovered that TXBUFE is probably the better signal to wait for, because sometime I'll also use the next pointer.

Sorry if you have the feeling that I wasted your time. But to me it still seems not logical that ENDTX is asserted high by PDC while the TX transfer is disabled. Anyway, I need to live with it.

I now have another issue with USART in SPI slave mode. But that will be another question.

Regards

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