sama5d4 HSMC

Discussion around products based on ARM Cortex-A5 core.

Moderator: nferre

Jimmy.Zhu
Posts: 14
Joined: Mon Sep 14, 2015 9:15 am

sama5d4 HSMC

Sun Apr 10, 2016 5:23 pm

Hi guys,

There is FPGA device on my board, and I just can access 4K range data by HSMC external bus intface.But when I try to access the address exceed 4K, there will be no NRD NWE signal come out. I also test in UBOOT, and the result is the same. Would you give me some suggestions about this problem?

The iomem maped is 32K, devicetree node descrition as below:

Code: Select all

			smc: smc@fc05c600 {
				compatible = "atmel,sama5d4-smc";
				clocks = <&hsmc_clk>;
				xc6-irq-gpio = <&pioE 27 GPIO_ACTIVE_HIGH>;
				reg =  <
						0xfc05c600 0x000000ec
						0x10000000 0x00008000
						0x60000000 0x00008000
						0x70000000 0x00008000
					   >;
			
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_smc_d8_d16 &pinctrl_smc_a0_a15 &pinctrl_smc_ncs0 
							 &pinctrl_smc_ncs1 &pinctrl_smc_ncs2 &pinctrl_smc_nwr1_nbs1 &pinctrl_smc_nwait>;
				status = "okay";

			};
Thanks
dlad
Posts: 20
Joined: Mon Jul 27, 2015 4:27 pm

Re: sama5d4 HSMC

Wed Apr 13, 2016 1:45 pm

Hello,
I'll answer you in your topic rather than mine.
I don't have access to our custom board for the moment so I'll give you an output of my registers later and the init from the devicetree & U-boot.

You should check the register PIOE PSR (0xFFFFFA08) from your kernel (not from U-boot)
Ensure all addresses pins are declared as active.
Do the same check with NRD, NWE and CS.

Also check the physical address you give to your FPGA. Do you check if your 32K are fully available in the memory map of the device ? (e.g not share with another memory or something else).

Edit: Addresses pins are on port E on the sama5d3 but I don't know for sama5d4
dlad
Posts: 20
Joined: Mon Jul 27, 2015 4:27 pm

Re: sama5d4 HSMC

Thu Apr 14, 2016 1:52 pm

Hi,

I take a quick look to the HSMC_WPMR (0xFFFFC6E4 from datasheet SAMA5D3). result is 0.

Here are my init from U-boot & devicetree of my FPGA (CS1 is used to access it).
It is almost the same init as the NAND in U-boot

Code: Select all

	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;

	at91_periph_clk_enable(ATMEL_ID_SMC);
	
	/* Configure SMC CS1 for MMC */
	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
	       &smc->cs[1].setup);
	writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(11) |
	       AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(11),
	       &smc->cs[1].pulse);
	writel(AT91_SMC_CYCLE_NWE(11) | AT91_SMC_CYCLE_NRD(14),
	       &smc->cs[1].cycle);
	writel(AT91_SMC_TIMINGS_TCLR(0) | AT91_SMC_TIMINGS_TADL(0)  |
	       AT91_SMC_TIMINGS_TAR(0)  | AT91_SMC_TIMINGS_TRR(0)   |
	       AT91_SMC_TIMINGS_TWB(0)  | AT91_SMC_TIMINGS_RBNSEL(0)|
	       AT91_SMC_TIMINGS_NFSEL(0), &smc->cs[1].timings);
	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
	       AT91_SMC_MODE_EXNW_DISABLE |
	       AT91_SMC_MODE_DBW_8 |
	       AT91_SMC_MODE_TDF_CYCLE(1),
	       &smc->cs[1].mode);

	/* Address pin (A0 ~ A11) configuration */
	at91_set_a_periph(AT91_PIO_PORTE, 0, 0);
	at91_set_a_periph(AT91_PIO_PORTE, 1, 0);
	at91_set_a_periph(AT91_PIO_PORTE, 2, 0);
	at91_set_a_periph(AT91_PIO_PORTE, 3, 0);
	at91_set_a_periph(AT91_PIO_PORTE, 4, 0);
	at91_set_a_periph(AT91_PIO_PORTE, 5, 0);
	at91_set_a_periph(AT91_PIO_PORTE, 6, 0);
	at91_set_a_periph(AT91_PIO_PORTE, 7, 0);
	at91_set_a_periph(AT91_PIO_PORTE, 8, 0);
	at91_set_a_periph(AT91_PIO_PORTE, 9, 0);
	at91_set_a_periph(AT91_PIO_PORTE, 10, 0);
	at91_set_a_periph(AT91_PIO_PORTE, 11, 0);
	/* CS1 pin configuration */
	at91_set_a_periph(AT91_PIO_PORTE, 27, 0);
Devicetree :

Code: Select all

fpga0: fpga@40000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x40000000 0x1000>;
		status = "okay"
		};

		nand0: nand@60000000 {
			nand-bus-width = <8>;
			nand-ecc-mode = "hw";
			atmel,has-pmecc;
			atmel,pmecc-cap = <4>;
			atmel,pmecc-sector-size = <512>;
			nand-on-flash-bbt;
			status = "okay";
note: NAND and FPGA declarations are in the same node

Regards
Jimmy.Zhu
Posts: 14
Joined: Mon Sep 14, 2015 9:15 am

Re: sama5d4 HSMC

Mon Apr 18, 2016 7:02 am

dlad wrote:Hi,

I take a quick look to the HSMC_WPMR (0xFFFFC6E4 from datasheet SAMA5D3). result is 0.

Here are my init from U-boot & devicetree of my FPGA (CS1 is used to access it).
It is almost the same init as the NAND in U-boot

Code: Select all

	struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;

	at91_periph_clk_enable(ATMEL_ID_SMC);
	
	/* Configure SMC CS1 for MMC */
	writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
	       AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
	       &smc->cs[1].setup);
	writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(11) |
	       AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(11),
	       &smc->cs[1].pulse);
	writel(AT91_SMC_CYCLE_NWE(11) | AT91_SMC_CYCLE_NRD(14),
	       &smc->cs[1].cycle);
	writel(AT91_SMC_TIMINGS_TCLR(0) | AT91_SMC_TIMINGS_TADL(0)  |
	       AT91_SMC_TIMINGS_TAR(0)  | AT91_SMC_TIMINGS_TRR(0)   |
	       AT91_SMC_TIMINGS_TWB(0)  | AT91_SMC_TIMINGS_RBNSEL(0)|
	       AT91_SMC_TIMINGS_NFSEL(0), &smc->cs[1].timings);
	writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
	       AT91_SMC_MODE_EXNW_DISABLE |
	       AT91_SMC_MODE_DBW_8 |
	       AT91_SMC_MODE_TDF_CYCLE(1),
	       &smc->cs[1].mode);

	/* Address pin (A0 ~ A11) configuration */
	at91_set_a_periph(AT91_PIO_PORTE, 0, 0);
	at91_set_a_periph(AT91_PIO_PORTE, 1, 0);
	at91_set_a_periph(AT91_PIO_PORTE, 2, 0);
	at91_set_a_periph(AT91_PIO_PORTE, 3, 0);
	at91_set_a_periph(AT91_PIO_PORTE, 4, 0);
	at91_set_a_periph(AT91_PIO_PORTE, 5, 0);
	at91_set_a_periph(AT91_PIO_PORTE, 6, 0);
	at91_set_a_periph(AT91_PIO_PORTE, 7, 0);
	at91_set_a_periph(AT91_PIO_PORTE, 8, 0);
	at91_set_a_periph(AT91_PIO_PORTE, 9, 0);
	at91_set_a_periph(AT91_PIO_PORTE, 10, 0);
	at91_set_a_periph(AT91_PIO_PORTE, 11, 0);
	/* CS1 pin configuration */
	at91_set_a_periph(AT91_PIO_PORTE, 27, 0);
Devicetree :

Code: Select all

fpga0: fpga@40000000 {
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x40000000 0x1000>;
		status = "okay"
		};

		nand0: nand@60000000 {
			nand-bus-width = <8>;
			nand-ecc-mode = "hw";
			atmel,has-pmecc;
			atmel,pmecc-cap = <4>;
			atmel,pmecc-sector-size = <512>;
			nand-on-flash-bbt;
			status = "okay";
note: NAND and FPGA declarations are in the same node

Regards

Hi Dlad,
Thank you very much!
HSMC 4K limitation issue is fixed now! Firstly I find the issue in kernel driver, then I back to U-Boot to test, initialize HSMC,use command 'md' to read FPGA data from SMC bus, and the result is the same which there will be no NRD NWE signal when read the address exceed 4K.

At last, I turn to boostrap, and fixed the issue.
It's the default confuration of MATRIX H32MX for EBI, In boostrap, the default configuration of EBI make the low 4K bytes is non-secure, and the left is secure, so it's invald to read the secure address exceed 4K.

So I follow region6,simply configure the region0-region5, then it's OK!

Code: Select all

319     /* 12:  Bridge from H64MX to H32MX */
320
321     /*
322      * Matrix 1 (H32MX)
323      */
324
325     /* 0: Bridge from H32MX to H64MX: Not Secured */
326
327     /* 1: H32MX Peripheral Bridge 0: Not Secured */
328
329     /* 2: H32MX Peripheral Bridge 1: Not Secured */
330
331     /*
332      * 3: External Bus Interface
333      * EBI CS0 Memory(256M) ----> Slave Region 0, 1
334      * EBI CS1 Memory(256M) ----> Slave Region 2, 3
335      * EBI CS2 Memory(256M) ----> Slave Region 4, 5
336      * EBI CS3 Memory(128M) ----> Slave Region 6
337      * NFC Command Registers(128M) -->Slave Region 7
338      *
339      * NANDFlash(EBI CS3) --> Slave Region 6: Non-Secure
340      */
341     srtop_setting = MATRIX_SRTOP(6, MATRIX_SRTOP_VALUE_128M);
342     srtop_setting |= MATRIX_SRTOP(7, MATRIX_SRTOP_VALUE_128M);
343     sasplit_setting = MATRIX_SASPLIT(6, MATRIX_SASPLIT_VALUE_128M);
344     sasplit_setting |= MATRIX_SASPLIT(7, MATRIX_SASPLIT_VALUE_128M);
345     ssr_setting = (MATRIX_LANSECH_NS(6)
346             | MATRIX_RDNSECH_NS(6)
347             | MATRIX_WRNSECH_NS(6));
348     ssr_setting |= (MATRIX_LANSECH_NS(7)
349             | MATRIX_RDNSECH_NS(7)
350             | MATRIX_WRNSECH_NS(7));
351     matrix_configure_slave_security(AT91C_BASE_MATRIX32,
352                     H32MX_EXTERNAL_EBI,
353                     srtop_setting,
354                     sasplit_setting,
355                     ssr_setting);

Jimmy.Zhu
Posts: 14
Joined: Mon Sep 14, 2015 9:15 am

Re: sama5d4 HSMC

Thu Apr 21, 2016 1:11 pm

I find that U-Boot also configure the MATRIX secure and non-secure region, may be I can fixed it in U-Boot.

In U-Boot the source file "arch/arm/cpu/armv7/at91/sama5d4_devices.c", there is a function matrix_init()

May be I can modify the U-Boot function to fixed the issue, but I haven't tried

below is the U-Boot function

Code: Select all

void matrix_init(void)
{
	struct atmel_matrix *h64mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX0;
	struct atmel_matrix *h32mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX1;
	int i;

	/* Disable the write protect */
	writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
	writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr);

	/* DDR port 1 ~ poart 7, slave number is: 4 ~ 10 */
	for (i = 4; i <= 10; i++) {
		writel(0x000f0f0f, &h64mx->ssr[i]);
		writel(0x0000ffff, &h64mx->sassr[i]);
		writel(0x0000000f, &h64mx->srtsr[i]);
	}

	/* CS3 */
	writel(0x00c0c0c0, &h32mx->ssr[3]);
	writel(0xff000000, &h32mx->sassr[3]);
	writel(0xff000000, &h32mx->srtsr[3]);

	/* NFC SRAM */
	writel(0x00010101, &h32mx->ssr[4]);
	writel(0x00000001, &h32mx->sassr[4]);
	writel(0x00000001, &h32mx->srtsr[4]);

	/* Configure Programmable Security peripherals on matrix 64 */
	writel(readl(&h64mx->spselr[0]) | 0x00080000, &h64mx->spselr[0]);
	writel(readl(&h64mx->spselr[1]) | 0x00180000, &h64mx->spselr[1]);
	writel(readl(&h64mx->spselr[2]) | 0x00000008, &h64mx->spselr[2]);

	/* Configure Programmable Security peripherals on matrix 32 */
	writel(readl(&h32mx->spselr[0]) | 0xFFC00000, &h32mx->spselr[0]);
	writel(readl(&h32mx->spselr[1]) | 0x60E3FFFF, &h32mx->spselr[1]);

	/* Enable the write protect */
	writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
	writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr);
}

Return to “SAMA5D Cortex-A5 MPU”

Who is online

Users browsing this forum: No registered users and 2 guests