Offsets for internal Galois tables (PMECC) of SAMA5D2

Discussion around products based on ARM Cortex-A5 core.

Moderator: nferre

gselabs
Posts: 23
Joined: Sun Feb 17, 2019 7:04 pm

Offsets for internal Galois tables (PMECC) of SAMA5D2

Wed Jun 26, 2019 12:48 pm

I am trying to configure atbootstrap for custom board based on SAMA5D27C-D1G. There is NAND as main storage media. I need to use Galois tables from the SoC ROM. I wonder, which offsets values I need to set for the following configuration parameters?

Code: Select all

#define CONFIG_LOOKUP_TABLE_ALPHA_OFFSET
#define CONFIG_LOOKUP_TABLE_INDEX_OFFSET

#define CONFIG_LOOKUP_TABLE_ALPHA_OFFSET_1024
#define CONFIG_LOOKUP_TABLE_INDEX_OFFSET_1024
There is only one evaluation board based on SAMA5D2 which uses NAND flash. It is PTC-EK board. But atbootstrap configuration for this board has the folowing configuration parameter:

Code: Select all

#define NO_GALOIS_TABLE_IN_ROM
SAMA5D2 series datasheet is not clear about the Galois tables offsets.

Code: Select all

For a full description and an example of how to use the PMECC detection and correction feature, see the
software package dedicated to this device on our website.
So how to configure atbootstrap to use the Galois tables from SoC's ROM?
blue_z
Location: USA
Posts: 1943
Joined: Thu Apr 19, 2007 10:15 pm

Re: Offsets for internal Galois tables (PMECC) of SAMA5D2

Sat Jun 29, 2019 1:45 am

gselabs wrote: SAMA5D2 series datasheet is not clear about the Galois tables offsets.

Code: Select all

For a full description and an example of how to use the PMECC detection and correction feature, see the
software package dedicated to this device on our website.
Why is this "not clear" to you?
Did you see the memory map following that excerpt?
Have you looked at the Software Package as suggested? (The most recent release, version 2.15, "add(s) system addresses of ROMs for PMECC tables".)

FYI I did a quick dump of the memory (using U-Boot) of a SAMA5D2 at the locations specified by the SoC datasheet (as well as the SoftPack), and the data seems to match the Galois field tables for 512-byte and 1024-byte sectors.

So the following should suffice for a SAMA5D2:

Code: Select all

#define CONFIG_LOOKUP_TABLE_INDEX_OFFSET	(0x40000)
#define CONFIG_LOOKUP_TABLE_ALPHA_OFFSET	(0x44000)

#define CONFIG_LOOKUP_TABLE_INDEX_OFFSET_1024	(0x48000)
#define CONFIG_LOOKUP_TABLE_ALPHA_OFFSET_1024	(0x50000)

Regards
gselabs
Posts: 23
Joined: Sun Feb 17, 2019 7:04 pm

Re: Offsets for internal Galois tables (PMECC) of SAMA5D2

Fri Jul 05, 2019 10:45 am

Thank you for your help.

It worth to be mentioned, but the file u-boot-at91/arch/arm/mach-at91/include/mach/sama5d2.h has no information of the tables offsets. Further more, there is the following define:

Code: Select all

/* No PMECC Galois table in ROM */
#define NO_GALOIS_TABLE_IN_ROM
Also the wiki page about PMECC configuration https://www.at91.com/linux4sam/bin/view ... cConfigure is outdated. There is no

Code: Select all

CONFIG_PMECC_INDEX_TABLE_OFFSET
U-Boot's configuration option any more.

So enabling PMECC on, for example, on a PTC-EK is not easy.

As far as I see, the modern SAMA5D chips don't use the following macros:

Code: Select all

CONFIG_SYS_NAND_ENABLE_PIN
CONFIG_SYS_NAND_READY_PIN
Why it is happend?

Return to “SAMA5D Cortex-A5 MPU”

Who is online

Users browsing this forum: No registered users and 1 guest