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SAMA5D27 System-In-Package with LPDDR2

Posted: Mon Jul 22, 2019 4:32 pm
by mikehaben
Hi all,
Does anyone have a tested-and-working design using one of the System-In-Package variants of SAMA5D27? Even better if it happens to be a LPDDR2 variant (SAMA5D27C-LD1G or -LD2G).
I am having no success getting the DDRAM-controller configured correctly and LPDDR2 working. I've engaged with Microchip Support and they've provided the latest (v2.16) version of their Software Package, but using the register-settings and initialisation sequence from that still doesn't make it work.
I've tried halving my clock-speeds, adding decoupling caps on supply-lines directly beneath the IC, making tentative modifications to the sequence of commands in the initialisation sequence, but none of these has made any difference to the values read back from MPDDRC registers.
We developed initially using the SOM1-EK dev board, and that went well, so we were hoping that the transition to the SIP-based board would be straightforward. At least hearing that _someone_ has made the LPDDR2 SIP variant work would give me some encouragement!

Mike Haben
ASH Wireless

Re: SAMA5D27 System-In-Package with LPDDR2

Posted: Mon Jul 22, 2019 11:18 pm
by blue_z
Have you tested with more than one SiP?

Re: SAMA5D27 System-In-Package with LPDDR2

Posted: Tue Jul 23, 2019 9:12 am
by mikehaben
Yes, tested 4 SIP boards, 4 different sets of values read back from the MPDDRC registers (consistently the same value for any one board). On two of them the "Device Auto-Initialisation" bit in MPDDRC_MR clears after a few usec as expected, on the other two it never clears. All 4 draw about the same current from 2 supplies.
One more board to try, once I've fixed an assembly fault...

Re: SAMA5D27 System-In-Package with LPDDR2

Posted: Tue Jul 23, 2019 10:18 am
by blue_z
To check-off another obvious item: have you used AT91Bootstrap version 3.8.13 (which was released 2 weeks ago)?

Here's a crazy idea to try:
Enable all the peripheral clocks you can, and then try the memory controller initialization.
Based on the experience of a nonresponsive peripheral is an unpowered one.


Re: SAMA5D27 System-In-Package with LPDDR2

Posted: Wed Jul 24, 2019 9:52 am
by mikehaben
Thanks, yes - all updated to 3.8.13

Tried a variation on your suggestion - disabled first the peripheral-clock for the MPDDRC and then the system-clock for the DRAM - in each case, results in all-zero (or all-FF) being read back from registers - so at least I'm confident that both of those are working, because with them both enabled I read back something at least slightly-related to what I've written.

Re: SAMA5D27 System-In-Package with LPDDR2

Posted: Wed Jul 31, 2019 11:21 am
by mikehaben
An update:
I've taken Atmel's own software package (from, created a new SAMA5D2 board-target "TABASCO" that #defines BOARD_DDRAM_TYPE AD220032D (as used in the SAMA5D27C-LD2G SIP), and built the "examples/ddram" executable. And... it reports:
-- DDRAM Example --
Softpack v2.16_plus_TABASCO
Built for TABASCO
Processor: SAMA5D27C-LD2G
Processor clock: 384 MHz
Master clock: 128 MHz
MMU is disabled
I-Cache is enabled
D-Cache is disabled
L2-Cache is disabled

-I- Starting memory validation of External DDRAM (256 MB)
-I- Buffer: 4096 bytes at 0x00210920
Error in range 0x20000000-0x20001000
Test Failed (passed=0, failed=1) (3ms)
Error in range 0x20000000-0x20001000
Test Failed (passed=0, failed=2) (4ms)
Error in range 0x20000000-0x20001000
Test Failed (passed=0, failed=3) (3ms)
... etc.

I was interested to note that the file target/sama5d2/chip.h, which contains extended-ID values for about a dozen different SAMA5D2x variants, does not (as at version 2.16) include the EXIDs for any of the system-in-package devices that incorporate LPDDR2 memory! So presumably the SoftPack has not been tested on any of those SIPs...

I've submitted my modified SoftPack code back to Microchip and asked them to test the DDRAM-test example on a known-good platform with AD2200xx LPDDR2 memory.

Re: SAMA5D27 System-In-Package with LPDDR2

Posted: Mon Aug 12, 2019 12:28 pm
by mikehaben
Believe we have found the problem - our prototype design lacks a DDR_VREF signal!

The SAMA5D2-series and SAMA5D2-SIP datasheets DS60001476C and DS60001484B do not properly describe this signal or how it should be generated. I have notified Microchip via the support case we already have open, hopefully the datasheets will be revised in due course.