SAMA5D2: How to use Integrity Check Monitor for ROM check?

Discussion around products based on ARM Cortex-A5 core.

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lrumanroe
Posts: 2
Joined: Mon Jan 20, 2020 8:18 pm

SAMA5D2: How to use Integrity Check Monitor for ROM check?

Mon Jan 20, 2020 9:32 pm

I am trying to get the Integrity Check Monitor to monitor a block of ROM on a custom board with the SAMA5d24 chip. The block of ROM is in DDR3 memory. Can the ICM monitor a block of read only memory? I implemented the crypto_icm example from the softpack, and it works as expected. I want to use the ICM in automatic monitoring mode and I cannot find any examples on how to do that on a block of ROM. I have taken the example code and tried to change modify it, but I lack a lot of understanding on how the ICM works. Here is my code:

// Reset and disable the ICM
mpst_icmRegs->ICM_CTRL = ICM_CTRL_SWRST;

mast_mainList[0].u32_startAddr = 0x20300000;
mast_mainList[0].u32_nextAddr = static_cast<uint8>(0);
mast_mainList[0].u32_cntrl = 0;
mast_mainList[0].u32_config = ICM_RCFG_WRAP | ICM_RCFG_CDWBN;



// Configure the ICM
mpst_icmRegs->ICM_CFG = ICM_CFG_UALGO_SHA1 | ICM_CFG_ASCD;

uint32 u32_addr = (uint32)&mast_mainList[0];
// Set the descriptor start address
mpst_icmRegs->ICM_DSCR = ICM_DSCR_DASA(u32_addr);
mpst_icmRegs->ICM_HASH = ((uint32_t)hash_addr);

mpst_icmRegs->ICM_IDR = 0xFFFFFFFF;

mpst_icmRegs->ICM_CTRL = ICM_CTRL_RMEN(ID_REGION0 | ID_REGION1 | ID_REGION2 | ID_REGION3);
mpst_icmRegs->ICM_IER = ICM_IER_RHC(ID_REGION0 | ID_REGION1 | ID_REGION2 | ID_REGION3);

mpst_icmRegs->ICM_CTRL = ICM_CTRL_ENABLE;

I do get a RHC(Region hash completed) interrupt , but I also get a RBE (Bus error) interrupt. Any idea why the bus error? Do I need a Hash address? If so what size hash? Does it need to be as big as the block of ROM? I did run it with a hash address and still go the bus error.
Also, TRSIZE in the Region control structure seems to be number of blocks - but I don't really see what size a block is?

Is there any documentation that gives me a more in depth information on how the ICM works?

Any help would be greatly appreciated.
Thank you,
Lacrecia
blue_z
Location: USA
Posts: 2033
Joined: Thu Apr 19, 2007 10:15 pm

Re: SAMA5D2: How to use Integrity Check Monitor for ROM check?

Tue Jan 21, 2020 4:15 am

lrumanroe wrote: I am trying to get the Integrity Check Monitor to monitor a block of ROM on a custom board with the SAMA5d24 chip. The block of ROM is in DDR3 memory.
Do not adapt standard nomenclature/acronym such as ROM to your own meaning.
Just because your application wants to restrict write access to a region of RAM does not transform that RAM into ROM.
Consequently your title makes no sense.

lrumanroe wrote: Here is my code:
What is the context of this code?

What you posted does not look to be a complete program.
If someone takes the time to scrutinize this code and points out that it is missing X, are you going to respond that you didn't post this X and it's handled in some other code?

You seem to be using structures of your own definitions for register offsets/addresses.
How have you validated these definitions?


lrumanroe wrote: // Reset and disable the ICM
mpst_icmRegs->ICM_CTRL = ICM_CTRL_SWRST;
Of the numerous peripherals that I have dealt with, I do not recall any that completed a software reset in one (or just a few) CPU instruction cycle(s).
Did you verify that the initialization (after the reset) was successful?


lrumanroe wrote: Is there any documentation that gives me a more in depth information on how the ICM works?
Yes, the SoC datasheet.
For something more basic: "What is ICM? How to Use the ICM For Cryptography".
There's also ASF documentation for the microcontroller implementations of ICM: "Quick Start Guide for the ICM driver" and "Integrity Check Monitor Controller (ICM)".

Regards
lrumanroe
Posts: 2
Joined: Mon Jan 20, 2020 8:18 pm

Re: SAMA5D2: How to use Integrity Check Monitor for ROM check?

Wed Jan 22, 2020 8:26 pm

Thank you for providing this list of documents. It is most helpful. I have the ICM working now.

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