ATSAMA5D27-WLSOM1-EK1: LPDDR2 Power-Off Sequence

Discussion around products based on ARM Cortex-A5 core.

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Marc7909
Posts: 18
Joined: Mon Apr 20, 2020 3:14 pm

ATSAMA5D27-WLSOM1-EK1: LPDDR2 Power-Off Sequence

Mon Apr 26, 2021 10:54 am

Hi,

We are trying to understand wether the power-off sequence is managed by the SOM or if we require to write software to handle this ourselves. I both read in the datasheet (SAMA5D2, WLSOM) that the power failure is handled at system level AND that it must be controlled by software. I could not find related posts and our tests lowering the voltage below the threshold does not shut down the SOM.

Any clarification would be appreciated
blue_z
Location: USA
Posts: 2157
Joined: Thu Apr 19, 2007 10:15 pm

Re: ATSAMA5D27-WLSOM1-EK1: LPDDR2 Power-Off Sequence

Thu Apr 29, 2021 1:46 am

Marc7909 wrote: I both read in the datasheet (SAMA5D2, WLSOM) that the power failure is handled at system level AND that it must be controlled by software.
Please provide the citations of these supposedly contradictory descriptions.

Regards
Marc7909
Posts: 18
Joined: Mon Apr 20, 2020 3:14 pm

Re: ATSAMA5D27-WLSOM1-EK1: LPDDR2 Power-Off Sequence

Mon May 03, 2021 11:56 am

SAMA5D27 Wireless SOM:

4.2.3.1 LPDDR2 Power-Off Sequence
>>> The LPDDR2 power-off sequence must be controlled by software to preserve the LPDDR2 device.
In this sequence, the CKE signal should be low during the full period the power rails are powering down.
>>> The power failure can be controlled by the embedded Voltage Supervisor (MIC842) and handled at system level (IRQ
on PD31). The LPDDR2 power-off sequence is applied using the bit LPDDR2_LPDDR3_PWOFF in the MPDDRC
Low-Power register (MPDDRC_LPR).

For more information, refer to the following documents:
• SAMA5D2 Series Data sheet available on https://www.microchip.com/, sections LPDDR2 Power Fail
Management and MPDDRC Low-Power Register
• Jedec Standard Low Power Double Data Rate 2 (LPDDR2), JESD209-2B
Note: An uncontrolled power-off sequence can be applied only up to 400 times in the life of an LPDDR2 device.

NOTE: Link not working in above statement
NOTE: providing an answer to the first question would have been ok too :)

Regards
nferre
Site Admin
Posts: 226
Joined: Wed Feb 14, 2007 11:17 am

Re: ATSAMA5D27-WLSOM1-EK1: LPDDR2 Power-Off Sequence

Tue May 04, 2021 9:26 am

Hi,

I'm a software guy, but last time I asked to my colleagues they were saying that on SAMA5D27 WLSOM1, the power down sequence applied to the LPDDR2 was preventing it to suffer from the unmanaged power loss issue. If you have qualified engineers, please check this aspect.
I know it's in contradiction with some warnings on the user guide, so if you cannot double-check on your side, I advice you to open a (free) support ticket on microchip.com website following this link:
http://support.microchip.com
Login to your "myMicrochip" account or creating one.
Then by clicking on "My Support" and finally "My Cases" button.

Regards,
Nicolas

***********************
AT91 Forums are moving to Microchip forum engine:
https://www.microchip.com/forums/f540.aspx
blue_z
Location: USA
Posts: 2157
Joined: Thu Apr 19, 2007 10:15 pm

Re: ATSAMA5D27-WLSOM1-EK1: LPDDR2 Power-Off Sequence

Wed May 05, 2021 3:46 am

Marc7909 wrote: Any clarification would be appreciated

>>> The LPDDR2 power-off sequence ...
>>> The power failure ...
Your confusion seems to be based on not distinguishing between a "LPDDR2 power-off sequence" (e.g. a `shutdown` directive) versus a "power failure", which is an unexpected loss of power.

The SAMA5D2 datasheet seems to describe the requirement IMO rather clearly in 8.2.4.1.1 LPDDR2 Power Fail Management:
The DDR power rail must be monitored externally and generate an interrupt when a power fail condition
is triggered. The interrupt handler must apply the sequence defined in the MPDDRC Low-power register
(MPDDRC_LPR) by setting bit LPDDR2_PWOFF (LPDDR2 Power Off bit).
So there are two components to LPDDR2 Power-Fail Management: first a hardware component (for an event detector), and second a software component (for an event handler).
(BTW your use of the phrase "system level" is confusing.)

The SAMA5D27-WLSOM1 does have the hardware capability to monitor the DDR power source.
A MIC842 voltage comparator is external to the SAMA5D27-SIP but part of the module.
The comparator's output pin is hardwired on the module to PD31 of the SAMA5D27-SIP for use as a "power-fail" interrupt.

You neglect to mention what Linux kernel version and branch that you are using.
However a quick review of various kernel sources seems to indicate that the software component of this "LPDDR2 Power-fail Sequence" may not be implemented.
Specifically I can find no Device Tree specification for use of pin PD31 as an interrupt source by a SAMA5D2.
Also the only use of the LPDDR2 Power-Off bit seems to be during a normal powerdown of a SAMA5D2.

Marc7909 wrote:NOTE: providing an answer to the first question would have been ok too
Actually your two posts have no questions (i.e. a query punctuated with a question mark).

Regards
Marc7909
Posts: 18
Joined: Mon Apr 20, 2020 3:14 pm

Re: ATSAMA5D27-WLSOM1-EK1: LPDDR2 Power-Off Sequence

Thu May 20, 2021 3:59 pm

Thank you for the added value blue_z.

For sake of completeness I am using the latest Linux4SAM 2020.10 kernel.

We are going to investigate further into this as our devices are subject to frequent unplugging,

Regards

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