dma channel always in busy state

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leo.ni
Posts: 52
Joined: Mon Jun 06, 2016 4:20 am

dma channel always in busy state

Mon Jun 06, 2016 4:37 am

Hi,all. i faced a problem about sama5d3 dmac.i used dmac to transfer data via ssc0 on sama5d3-xplained board, and after first transfer,the dma channel always in busy state,can someone give me some advise?Thanks for your help!
My config about ssc and dma:
DMA config:
static void _SscDmaTxSetup( void *pInstance )
{
assert( NULL != pInstance );

dataSource *pSource = (dataSource *)pInstance;
sDmaTransferDescriptor *pTds = dmaTdSSC0Tx;

Ssc* pSsc = _get_ssc_instance(pSource->dev.identify);
/* Setup TD list for TX */
pTds[0].dwSrcAddr = (uint32_t) sscTxBuffers[0];
pTds[0].dwDstAddr = (uint32_t) &pSsc->SSC_THR;
pTds[0].dwCtrlA = DMAC_CTRLA_BTSIZE(DATAPACKETSIZE)
| DMAC_CTRLA_SRC_WIDTH_BYTE | DMAC_CTRLA_DST_WIDTH_BYTE;
pTds[0].dwCtrlB = 0
| DMAC_CTRLB_SIF_AHB_IF0
| DMAC_CTRLB_DIF_AHB_IF2
| DMAC_CTRLB_FC_MEM2PER_DMA_FC
| DMAC_CTRLB_SRC_INCR_INCREMENTING
| DMAC_CTRLB_DST_INCR_FIXED;
pTds[0].dwDscAddr = (uint32_t) &pTds[1];

pTds[1].dwSrcAddr = (uint32_t) sscTxBuffers[1];
pTds[1].dwDstAddr = (uint32_t) &pSsc->SSC_THR;
pTds[1].dwCtrlA = DMAC_CTRLA_BTSIZE(DATAPACKETSIZE)
| DMAC_CTRLA_SRC_WIDTH_BYTE | DMAC_CTRLA_DST_WIDTH_BYTE;
pTds[1].dwCtrlB = 0
| DMAC_CTRLB_SIF_AHB_IF0
| DMAC_CTRLB_DIF_AHB_IF2
| DMAC_CTRLB_FC_MEM2PER_DMA_FC
| DMAC_CTRLB_SRC_INCR_INCREMENTING
| DMAC_CTRLB_DST_INCR_FIXED;
pTds[1].dwDscAddr = (uint32_t) &pTds[0];
CP15_coherent_dcache_for_dma ((uint32_t)pTds, ((uint32_t)pTds) + sizeof(pTds));
CP15_coherent_dcache_for_dma ((uint32_t)&sscTxBuffers[0], ((uint32_t)(&sscTxBuffers[0]) + DATAPACKETSIZE));
CP15_coherent_dcache_for_dma ((uint32_t)&sscTxBuffers[1], ((uint32_t)(&sscTxBuffers[1]) + DATAPACKETSIZE));
}


ssc config:
SSC_Configure( pSSC,
dir, //0:slave not gen clk 1:gen clk
mclk
);

tcmr.cks = 0 ; // 0:MCK 1:RK 2:TK
rcmr.cks = 1 ; // 0:MCK 1:TK 2:RK

tcmr.cko = 1 ; // 0:input only 1:continus 2:only transfer
rcmr.cko = 0 ; // 0:input only 1:continus 2:only transfer

tcmr.cki = 0; // 0: falling egde send
rcmr.cki = 0; // 1: rising edge lock

tcmr.start = 0; // 4: falling edge trigger for low left, 5: rising edge trigger for high left,
rcmr.start = 0; //0:continuous 1:transmit 2:RF_LOW 3:RF_HIGH 4:RF_FAILLING
//5:RF_RISING 6:RF_LEVEL 7:RF_EDGE 8:CMP_0
tcmr.sttdly = 0;
rcmr.sttdly = 0;

tcmr.period = 0; // period ; slave not use 0-->15
rcmr.period = 0; // period ; slave not use

tcmr.ckg = 0 ; //slave not use
rcmr.ckg = 0 ; //slave not use

tfmr.fsos = 0 ; //input only
rfmr.fsos = 0 ; //input only

tfmr.datnb = slot_num-1; //5 ; //6 slot TDM
rfmr.datnb = slot_num-1; //5 ;

tfmr.datlen = slot_len-1; //31 ; //32bits
rfmr.datlen = slot_len-1; //31 ;

tfmr.fslen = 0 ; //frame sync is not used
rfmr.fslen = 0 ; //frame sync is not used

tfmr.fsedge = 1 ;
rfmr.fsedge = 1 ;

tfmr.msbf = 1 ;
rfmr.msbf = 1 ;

tfmr.datdef = 0 ;
tfmr.fsden = 0 ;

rfmr.loop = 1 ; //0:normal 1:loop

SSC_ConfigureTransmitter( pSSC, tcmr.value, tfmr.value );
SSC_ConfigureReceiver( pSSC, rcmr.value , rfmr.value );

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