SAM S70 USB and Cortex-M7 instruction interference??

Discussions around product based on ARM Cortex M7 core.

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Posts: 12
Joined: Thu Jul 02, 2015 3:33 pm

SAM S70 USB and Cortex-M7 instruction interference??

Thu Dec 15, 2016 6:20 pm

Hi folks!

I've spent my last 3 days figuring out a VERY WEIRD failure... I wouldn't ever tought that such can be.

The symptom in short words: I have a not very complex project with a SAM S70 MCU. It uses USB (host), LCD and SDRAM through the EBI and some other. I have a micro OS (own one) and some threads running. The USB host gets pixels from a camera, 12 bits each, packed. These frames are processed and displayed on LCD.
This worked quite well for half a year now, then I started to optimize things and use SIMD instructions of the CPU.
As soon as I subtract a possibly higher value from the pixels than they are, using the UQSUB16 instrutction (so it saturates to 0), the USB host does a pipe interrupt with 3 or 4 error flags set, within some seconds or minutes. (The camera driver goes to "error" mode.)

So I tried some things:
- Set the MATRIX priorities etc. for the USB and the core. The throughput is very high (150 MHz MCK), so I did not expect enything from this.
- Disabled all my EBI accesses (live view, LCD refresh), except when receiving the frame and unpacking the pixels.
- Tried to subtract a value of 0 or 1. In this configuration, everything is free of error and runs for infinite time... (the pixels have a minimum value of 1, thats why)
- If I subtract a value of 16, the failure pops up in only after an hour. The higher value I subtract (and so the possibility for a saturation to zero is growing), the earlier I can get the failure.
- If I add a value (UQADD16) to the pixels (even with saturation to 65535), there is no failure.

I have implemented the pixel processing in C (with intrinsic function) and in assembly too, with the same result.

How can it be, that a single CPU instruction affects the function of the USB host??? These should be totally independent!

Some more details:
- USB transfers the data with DMA to the SDRAM
- CPU processes the incoming data from SDRAM back to SDRAM (diff. addr.) (cache is enabled)
- The clock setting is 300/150 MHz. It is stable from the beginnings, MCU power is sufficient, the sensible ones are filtered.

Thanks for ANY ideas! I am totally lost yet...
Posts: 7
Joined: Thu Jun 23, 2016 2:33 pm

Re: SAM S70 USB and Cortex-M7 instruction interference??

Mon Dec 19, 2016 12:41 pm

Thanks for ANY ideas! I am totally lost yet...
Perhaps an indirect influence by some side effects ? Neither can I see any direct correlation.

My first guess would be, some task/interrupt routine exceeds the scheduled runtime because of a different execution path (error handling ?) somewhere. That might cause overruns/losses.

My second guess would be a race condition. Something a DMB/DSB or ISB instruction would probably fix.

But, as said, just guesses ...

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