AT91SAM3U4E IAR Workbench 5.4, Linker configuration file

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AT91SAM3U4E IAR Workbench 5.4, Linker configuration file

Sun Feb 13, 2011 11:53 am

Hi everybody,
I am using an AT91SAM3U4E and the IAR EWARM 5.4 embedded workbench for compilation purpose with Segger JLINK- JTAG (ICE) for debugging.
The output converter of the IAR workbench generates a *.sim file, because my bootloader shall copy the application according to the sim- file description from an external flash into the internal flash regions. The bootloader is located in the internal flash region. The internal flash regions of the Cortex are Flash_0: 0x80000  0x9FFFF; Flash_1: 0x100000  0x11FFFF) .The copy procedures of the bootloader are located in RAM.
If the application becomes to big (Application>Internal flash size) an additional region is intended in the external flash for execution in place (XIP). The output when using the output converter after compilation of my application is as follows: (The application starts at address 0x84000)
Dumping 192346 code bytes
Entry address: 0x96929
Data record - address: 0x84000
size: 0x12F4C
Data record - address: 0x60010000
size: 0x1C00E
Checksum: 0xFED7F25E

As you can see the second internal flash region is not used, but the external flash region is used for code (0x60010000). That’s the problem, because at first the internal flash regions shall be filled with code. I am not able to configure the linker configuration file to do that… ! I already tried to use the block directive...
Probably you could help me…

Thank you for helping...

Here is my liker configuration file:

/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */

define symbol __ICFEDIT_intvec_start__ = 0x00084000;
/*-Memory Regions-*/

define symbol __ICFEDIT_region_ROM0_start__ = 0x00084000;
define symbol __ICFEDIT_region_ROM0_end__ = 0x0009FFFF;
define symbol __ICFEDIT_region_ROM1_start__ = 0x00100000;
define symbol __ICFEDIT_region_ROM1_end__ = 0x0011FFFF;
define symbol __ICFEDIT_region_ROM2_start__ = 0x60010000;
define symbol __ICFEDIT_region_ROM2_end__ = 0x6004FFFF;
define symbol __ICFEDIT_region_RAM0_start__ = 0x20000000;
define symbol __ICFEDIT_region_RAM0_end__ = 0x20007FFF;
define symbol __ICFEDIT_region_RAM1_start__ = 0x20080000;
define symbol __ICFEDIT_region_RAM1_end__ = 0x20083FFF;
define symbol __ICFEDIT_region_EXTSRAM_start__ = 0x61000000;
define symbol __ICFEDIT_region_EXTSRAM_end__ = 0x610FFFFF;

define symbol __ICFEDIT_size_cstack__ = 0x1000;
define symbol __ICFEDIT_size_heap__ = 0x100;
/**** End of ICF editor section. ###ICF###*/

define memory mem with size = 4G;
/* Description of flash regions*/
define region ROM_region = mem:[from __ICFEDIT_region_ROM0_start__ to __ICFEDIT_region_ROM0_end__] | mem:[from __ICFEDIT_region_ROM1_start__ to __ICFEDIT_region_ROM1_end__] | mem:[from __ICFEDIT_region_ROM2_start__ to __ICFEDIT_region_ROM2_end__];
/* Description of RAM regions*/
define region RAM_region = mem:[from __ICFEDIT_region_RAM0_start__ to __ICFEDIT_region_RAM0_end__] | mem:[from __ICFEDIT_region_RAM1_start__ to __ICFEDIT_region_RAM1_end__] | mem:[from __ICFEDIT_region_EXTSRAM_start__ to __ICFEDIT_region_EXTSRAM_end__];

define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };

initialize by copy { readwrite };
do not initialize { section .noinit };

place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };

place in ROM_region { readonly };

place in RAM_region { readwrite,
block CSTACK,
block HEAP };

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