Bare Metal FIQ

Discussion around products based on ARM Cortex-A5 core.

Moderator: nferre

Posts: 25
Joined: Wed Jul 30, 2014 9:17 pm

Bare Metal FIQ

Wed Nov 05, 2014 11:21 am

I am trying to implement a FIQ handler in Bare Metal, using the SAMA5d3x coude sourcery.

I am configuring the AIC as follows:

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    // for testing, enable the FIQ
    pAIC->u32AIC_SSR  = ID_FIQ;
    pAIC->u32AIC_SMR  = 0x00000000;	///< edge triggered
    pAIC->u32AIC_SVR  = (uint32_t) &testFiqHandler;
    pAIC->u32AIC_IECR = 0x00000001;
The command at address 0x0000001C is the branch to FIQ vector address:

Code: Select all

ldr pc, [pc, #-0xF20]
reading the FIQ vector address from address 0xFFFFF104.

I see inside the AIC that the SVR for Interrupt source 0 (FIQ) is correctly set to point at my FIQ handler function.

When i start debugging and set a breakpoint at 0x0000001C, I see that the execution stops there.

But if continuoing in "Single Instruction Execution", I see that the execution is not branching into the FIQ handler funtion, but branching to address 0x00000000 and stopping at address 0x00000004 in a endless loop (guess that this is a non initialised exeption vector).

Question: Why is the FIQ not branching into the FIQ handler function?

Question: Alternatively the Data Sheet suggests to directly map the FIQ handler function to address 0x0000001C. Is there an easy way to map the function to the fixed address, especially using the code sourcery libs?
Posts: 25
Joined: Wed Jul 30, 2014 9:17 pm

Re: Bare Metal FIQ

Thu Nov 06, 2014 3:41 pm

Update: FIQ seems to work, if replacing the ldr command on address 0x0000001C with direct branch into FIQ handler.

For testing I am just toggling PIOB 28. Still on my scope then I see that the occurence of the FIQ handler jitters very much, compared to the rising edge that triggers the FIQ. It occurs from 100ns to 20us after edge. Does anybody know why the jitter is so big? I think, that FIQ calls should be more stable in time than IRQs. If realsing the same with normal IRQ and priority 7 i have a defined time from edge to IRQ handler of 1.5us that does not jitter at all.

Furthermore if activating priority 7 for the FIQ, ig gets better and jitter is only between 100ns and 2us. This is confusing, as the data sheet says, that FIQ does not use priority control as it breaks into all active other IRQs.

Finally I want a DMAC IRQ to trigger the FIQ by using Fast Forcing. But if activating Fast Forcing for the DMAC IRQ and avoiding external FIQs on FIQ pin, NO FIQ occurs at all, hence I think that Fast Forcing does not work.

Question: Is the FIQ on SAMA5d3 realy working at all?

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