LPDDR2 mode register write behavior

Discussion around products based on ARM Cortex-A5 core.

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LPDDR2 mode register write behavior

Wed Dec 10, 2014 8:58 am

SAMA5D36 with Micron MT42L128M32D1 LPDDR2.

I don't understand how the A5 generates the correct mode register write (MRW) sequence. On the Micron datasheet, that is two cycles on the CMD lines with 8 bits of MA0..7 and 8 bits of OP0..7 spread among the two cycles.

The MRS value in the MPDDRC_MR register does the MA0..7 bits, but where do the OP0..7 bits come from?

The sample code Atmel provides isn't working on our board, and they don't seem to ever set the mode register OP bits anywhere. Is it magic?

Also, is there a way to do a mode register read (MRR) command and get the data generally? Say to read vendor ID, rev ID, etc, from the LPDDR2. Anybody know how?

Atmel used to be better about documenting these things, sigh.


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