TWI issues

[friesen]

I can't seem to get something right with the TWI(flexcom if it makes a difference).

For some reason, the first and second write/read do not work correctly, then the following are. The very first rtcc address write it is not happening per the logic analyzer.

Code: Select all

#define CLOCK_BUS_ADDR (0xD0)
static RTCC static_clock_data __attribute__((aligned(32), section(".region_nocache")));
static struct _twi_desc tw = { .addr = FLEXTWI2, .freq = 100000, .slave_addr =
		CLOCK_BUS_ADDR >> 1, .transfer_mode = BUS_TRANSFER_MODE_POLLING, .timeout = 0, .use_fifo = true,
		.taskyield = { .method = while_wait_yield, .arg = 0 } };

static bool IsReady = false;
void ReadRTCC(RTCC * TimeVal) {

	xSemaphoreTake(BusMutex, portMAX_DELAY);
	{
		if (!IsReady) {
			twid_configure(&tw);
			IsReady = true;
		}
		struct _buffer buf[] = { { .data = (unsigned char*) "\0", .size = 1,
				.attr = (int) BUS_BUF_ATTR_TX | BUS_I2C_BUF_ATTR_START }, {
				.data = (unsigned char*) &static_clock_data, .size =
						sizeof(RTCC), .attr = (int) BUS_BUF_ATTR_RX
						| BUS_I2C_BUF_ATTR_START | BUS_I2C_BUF_ATTR_STOP } };
		twid_transfer(&tw, buf, 2, NULL);
		memcpy((unsigned char*) TimeVal, (unsigned char*) &static_clock_data,
				sizeof(RTCC));
	}
	xSemaphoreGive(BusMutex);
}

Unfortunately I am not allowed to post the captures. Essentially, buf[0] doesn't get sent at all the first try, and on the second, two 0 bytes get sent with a write.

[friesen]

It appears to be a bug in either silicon or the atmel software package framework.

Apparently sending a restart without checking for twi_is_byte_sent() corrupts the first outbound.

change _twid_poll_write

Code: Select all

	if (size == (buffer->size - 1)) {
		if (_check_tx_timeout(desc))
			return -ETIMEDOUT;
		twi_write_byte(desc->addr, buffer->data[i]);
		while(!twi_is_byte_sent(desc->addr));//<<---- Adding this line fixes, or suggest better
	}