SPI witch DMA

Discussion around product based on ARM Cortex M3 core.

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misterC
Posts: 3
Joined: Thu Dec 10, 2009 10:14 am

SPI witch DMA

Wed May 19, 2010 8:12 pm

hi

I would like to use SPI with DMA but SPI doesn´t have PDC then i ´doing this

AT91S_HDMA_CH * pDMA2= AT91C_BASE_HDMA_CH_2;


main()
{
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_HDMA;
pDMA2->HDMA_SADDR=(unsigned int)&pSPI0->SPI_RDR;
pDMA2->HDMA_DADDR=(unsigned int)SpiBuf;
pDMA2->HDMA_CTRLA=0x11000FFF;//(0x9 << 0)|(0x0 << 16)|(0x0 << 20)|(0x1 << 24)|(0x1 << 28);
pDMA2->HDMA_CTRLB=0x02510000;//(0x1 << 16)|(0x1 << 20)|(0x1 << 24)|(0x1 << 28);
pDMAC->HDMA_SREQ=(0x1 << 4);
//pDMA2->HDMA_CFG=0x0000;
AT91C_BASE_HDMA->HDMA_EBCIER=(1<<2);
while((pDMAC->HDMA_EBCISR & AT91C_HDMA_BTC2 ));

pDMAC->HDMA_EN = (1<<0);
pDMAC->HDMA_CHER = (1<<2);
}
anyone ever used the DMA sam3 without PDC. I am shorting Mosier and miso signal to store a buffer for dma.

thanks

I hope you can help
bm31416
Posts: 7
Joined: Wed Mar 17, 2010 4:14 pm

Re: SPI witch DMA

Mon Jul 19, 2010 4:06 pm

So, whats the problem?? Did you solve it?
bm31416
Posts: 7
Joined: Wed Mar 17, 2010 4:14 pm

Re: SPI witch DMA

Thu Jul 29, 2010 10:08 am

I got it working... down here is the source code if someone is need of help..


//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
void Config_DMA_SPI (void)
{
AT91C_BASE_PMC->PMC_PCER |= 1 << AT91C_ID_HDMA;
AT91C_BASE_HDMA->HDMA_GCFG=0;

//SPI RX

AT91C_BASE_HDMA_CH_0->HDMA_CTRLB = AT91C_HDMA_SRC_DSCR_FETCH_DISABLE |
AT91C_HDMA_DST_DSCR_FETCH_DISABLE |
AT91C_HDMA_SRC_ADDRESS_MODE_FIXED |
AT91C_HDMA_DST_ADDRESS_MODE_INCR |
AT91C_HDMA_FC_PER2MEM;

AT91C_BASE_HDMA_CH_0->HDMA_CFG = AT91C_HDMA_SRC_PER_2 |
AT91C_HDMA_LOCK_IF_DISABLE |
AT91C_HDMA_LOCK_B_DISABLE |
AT91C_HDMA_SRC_H2SEL_HW |
AT91C_HDMA_DST_H2SEL_SW |
AT91C_HDMA_FIFOCFG_LARGESTBURST;

AT91C_BASE_HDMA_CH_0->HDMA_DSCR=0;
AT91C_BASE_HDMA_CH_0->HDMA_SADDR=(unsigned int)&AT91C_BASE_SPI0->SPI_RDR;
AT91C_BASE_HDMA_CH_0->HDMA_DADDR=(unsigned int)buff_in;

AT91C_BASE_HDMA_CH_0->HDMA_CTRLA = AT91C_HDMA_DCSIZE_1 |
AT91C_HDMA_SCSIZE_1 |
AT91C_HDMA_SRC_WIDTH_BYTE |
AT91C_HDMA_SRC_WIDTH_BYTE |
TRANSFER_SIZE;

// SPI TX

AT91C_BASE_HDMA_CH_1->HDMA_CTRLB = AT91C_HDMA_SRC_DSCR_FETCH_DISABLE |
AT91C_HDMA_DST_DSCR_FETCH_DISABLE |
AT91C_HDMA_SRC_ADDRESS_MODE_FIXED |
AT91C_HDMA_DST_ADDRESS_MODE_FIXED |
AT91C_HDMA_FC_MEM2PER ;

AT91C_BASE_HDMA_CH_1->HDMA_CFG = AT91C_HDMA_DST_PER_1 |
AT91C_HDMA_SOD_DISABLE |
AT91C_HDMA_LOCK_IF_DISABLE |
AT91C_HDMA_LOCK_B_DISABLE |
AT91C_HDMA_SRC_H2SEL_SW |
AT91C_HDMA_DST_H2SEL_HW |
AT91C_HDMA_FIFOCFG_LARGESTBURST;

AT91C_BASE_HDMA_CH_1->HDMA_DSCR = 0;
AT91C_BASE_HDMA_CH_1->HDMA_SADDR=(unsigned int)&dummy_spi_byte;
AT91C_BASE_HDMA_CH_1->HDMA_DADDR=(unsigned int)&AT91C_BASE_SPI0->SPI_TDR;
AT91C_BASE_HDMA_CH_1->HDMA_CTRLA = AT91C_HDMA_DCSIZE_1 +
AT91C_HDMA_SCSIZE_1 +
AT91C_HDMA_SRC_WIDTH_BYTE +
AT91C_HDMA_DST_WIDTH_BYTE +
TRANSFER_SIZE;

//Interrupt
AT91C_BASE_HDMA->HDMA_EBCIER=AT91C_HDMA_BTC0+AT91C_HDMA_BTC1;
IRQ_ConfigureIT(AT91C_ID_HDMA, 0, HDMA_IrqHandler);


}
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
void Enable_DMA_SPI(void)
{
AT91C_BASE_HDMA_CH_0->HDMA_DADDR=(unsigned int)buff_in; // RX
AT91C_BASE_HDMA_CH_0->HDMA_CTRLA |= TRANSFER_SIZE;
AT91C_BASE_HDMA_CH_1->HDMA_CTRLA |= TRANSFER_SIZE;
AT91C_BASE_HDMA->HDMA_EN = AT91C_HDMA_ENABLE;

AT91C_BASE_HDMA->HDMA_CHER = AT91C_HDMA_ENA0_1; //RX
AT91C_BASE_HDMA->HDMA_CHER = AT91C_HDMA_ENA1_1; //TX
IRQ_EnableIT(AT91C_ID_HDMA);
}

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